1. Field of the Invention
The exemplary embodiments disclosed herein relate to a semiconductor package, and more particularly, to a stack semiconductor package and a method of manufacturing the same.
2. Description of the Related Art
A general stack package has a structure in which a plurality of substrates is stacked one atop another. The stacked package may include stacked semiconductor chip substrates. Each of the semiconductor chip substrates may be an integrated circuit itself or a package substrate including an integrated circuit chip mounted on a printed circuit board (PCB). Connection pads may be formed in the semiconductor chip substrates. The semiconductor chip substrates may be electrically connected to each other by connecting the connection pads with a bonding wire.
However, since a general stack semiconductor package has a structure in which a plurality of semiconductor chips is stacked, it has a limitation in reducing a size of a semiconductor package. Moreover, when an interposer such as a solder bump or an printed circuit substrate (PCB) is disposed between the semiconductor chip package substrates, the stack package has a complicated interconnection structure and it is difficult to reduce a size of the stack package because each of the solder bumps and the printed circuit bumps has to be connected to interconnection patterns.